SK Hynix presented a shared memory pool concept on November 12, 2026, at the Intel AI Summit in Seoul, allowing multiple AI servers to draw on a common memory reserve instead of each having a private one. The design, developed with Intel and other partners, moves high-capacity memory into dedicated racks accessible over fast interconnects such as Compute Express Link (CXL) and RDMA, alongside rather than replacing existing server setups. Its main target is the KV cache, which grows quickly during multi-turn inference: SK Hynix’s internal tests showed a time to first token of 80.76 seconds with eviction and recompute, falling to 15.45 seconds with remote CXL DRAM, an roughly 81% reduction in first-token latency, though these results are not yet validated with Intel and customers. The project builds on an existing partnership: in December 2025, SK Hynix became the first vendor to receive Intel Data Center certification for a 256 GB DDR5 RDIMM on the Xeon 6 platform, delivering up to a 16% increase in inference performance and cutting power consumption by about 18%. SK Hynix frames Intel’s CPUs as orchestrators in agentic AI systems, with GPUs handling heavy computation and pooled memory holding the growing context.
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