TSMC, the world’s largest chipmaker, is developing a packaging technology called CoPoS (Chip-on-Panel-on-Substrate) that replaces traditional circular wafers with rectangular panels measuring 310×310 mm. This innovation aims to increase usable surface area per production unit and directly challenge Intel’s EMIB platform in the race to package increasingly powerful AI processors. Pilot production reportedly began in June 2026 at VisEra’s Longtan plant in Taiwan, with mass production expected in the second half of 2028 or possibly 2029. TSMC’s current CoWoS platform is booked through 2027, creating a bottleneck that affects the entire AI sector, including crypto mining operations.
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